De-emphasis system and method for coupling digital signals through capacitively loaded lines

ABSTRACT

A system for de-emphasizing digital signals, such as address signals, boosts the level of the signals for one clock period prior to transmitting the signals through signal lines that may have a relatively large capacitance. The system may include a delay circuit that delays the digital signal for a period corresponding to one period of a clock signal. The system may also include a first multiplier circuit that generates a first intermediate signal by multiplying the first and second logic levels of the digital signal by a first multiplier. Similarly, a second multiplier circuit generates a second intermediate signal by multiplying the first and second logic levels of the delayed signal from the delay circuit by a second multiplier. A combining circuit then subtracts the second intermediate signal from the first intermediate signal, and the resulting signal is level-adjusted to generate the de-emphasized signal.

TECHNICAL FIELD

This invention relates to digital integrated circuits, and, more particularly, to a system and method for adjusting the waveform of a digital signal before it is coupled though a highly capacitive line to make it easier to correctly detect the signal at a receiving device.

BACKGROUND OF THE INVENTION

As the operating speeds of electronic devices, such as memory devices, continues to increase, the timing of digital signals received by the devices has become ever more critical. For example, in a memory device, such as a dynamic random access memory (“DRAM”) device, command, address and write data signals are transmitted to the memory device by a memory controller, and read data signals are transmitted to the memory controller by the memory device. Conventional memory devices generally operate synchronously with a clock signal, which defines the times that the received signals are considered valid. As the operating speed of memory devices continues to increase, the period during which the command, address and write data signals received by the memory device are considered valid has become ever shorter. As a result, it has become more critical to control the timing at which these signal are received by memory devices.

The timing of digital signals, such as command, address and data signals, are adversely affected by “jitter,” which is high frequency phase noise that cause rapid changes in the timing at which transitions of the digital signal occur. Jitter can be caused by a number of sources, such as noise coupled to digital circuits along with a digital signal, which causes the switching time of the digital circuit to vary in a random manner. Jitter can also be caused by variations in the shape of digital signals coupled to digital circuits.

With reference to FIG. 1, a digital signal having the waveform shown by the dotted line may be applied into a signal line. When the digital signal is applied to the signal line, its signal levels vary between voltages 0 and V*. As shown in FIG. 1, the transmitted waveform has a 50% duty cycle between time t₀ and time t₂. A “double width” pulse then occurs starting at time t₂ followed by a return to the original waveform starting at time t₄. If the signal line is highly capacitive, the waveform received by a downstream electronic device may have the waveform shown by the solid line in FIG. 1. As a result of the combination of the high frequency of the signal and the high capacitance of the signal line, the received waveform never reaches the full amplitudes of the transmitted waveform. For example, the transmitted signal starts charging the capacitive signal line toward the voltage V* at time t₀, which is shown by the dotted arrow at time to. However, the amplitude of the received signal never reaches the level V* volts. Instead, it reaches the level V₁ at time t₁, at which time the transmitted signal starts discharging the signal line toward 0 volts, as again shown by the dotted arrow. Again, the amplitude of the received signal never reaches 0 volts. Instead, it reaches the level V₂ at time t₂, at which time the transmitted signal again starts charging the signal line. Thus, the capacitive signal line charges toward V* volts from V₂ volts, and it starts discharging toward 0 volts from V₁ volts.

The symmetrical, unvarying shape of the transmitted signal between times t₀-t₂, causes the received signal to cross the midpoint voltage M with the same delay after each corresponding edge of the transmitted signal. This can be seen by the uniform spacing between the dotted arrows and the immediately following solid arrows. As a result, a digital circuit that switches state at the midpoint voltage M will change state with a uniform delay after each transition of the signal applied to the signal line.

During the double width pulse starting at time t₂, the signal line is charged toward the voltage V* for a longer period of time. The received signal therefore reaches the amplitude V₃ volts at time t₄ at which time the signal line begins being discharged toward 0 volts. The received signal still crosses the midpoint voltage M with the same delay after the corresponding edge of the transmitted signal as shown by the solid arrow following the dotted arrow at time t₂. However, because the discharge of the signal line starts from V₃ volts rather than the lower amplitude of V₁ volts, it now crosses the midpoint voltage M with a much longer delay after the corresponding edge of the transmitted signal. The skew of the received signal can be seen by the increased spacing of the solid arrow immediately following the dotted arrow at time t4. This skew in the midpoint amplitude M crossing delay as function of the bit pattern of the transmitted signal can results in signal jitter at a circuit receiving the signal. As explained above, jitter can adversely affect the receiving circuit's ability to capture the correct pattern of the transmitted digital signal because the receiving circuit may register the incorrect bit from the received signal.

This jitter problem is particularly acute in coupling address signal to memory devices. Address signal are typically transmitted to a plurality of memory devices through a signal distribution tree. The relatively large size of the tree when a large number of memory devices are present makes the address lines highly capacitive. In fact, the jitter caused by the high capacitance of address signal trees can defeat the major reason for using a tree, i.e., to ensure that address signal transitions arrive at all of the memory devices at the same time. The memory devices in a system attempt to capture the address signals using a clock signal, which may also be coupled through a clock tree. Ideally, a transition of the clock signal used to capture the address signals occurs at the center of the address signal. However, jitter can cause timing skews that cause the clock signal transition to occur before or after a “window” or “eye” during which the address signals are valid. For example, as shown in FIG. 2, if a clock signal CLK does not cause each of several address signals A<0:9> to latch at the proper time, errors in the operation of the memory device may result. Thus, the timing skew of the clock signal CLK relative to the timing skews of the address signals A<0:9> must be limited to allow the CLK signal to latch each of the several address signals A<0:9>. As the data transfer rate increases, the duration of each eye E for which each address signal A<0>-A<9> is valid decreases by a corresponding amount, as will be understood by one skilled in the art. With further reference to FIG. 2, the solid lines indicate the ideal address signals A<0>, A<1>, and A<9> signals, and the dashed lines indicate the worst case potential time skew for each of these signals. The ideal address signals A<0>, A<1>, and A<9> are centered at the rising edge of the CLK signals. The eyes E during which the address signals A<0>, A<1>, and A<9> are valid are defined by time intervals t₀-t₃, t₁-t₄, and t₅-t₇, respectively. In fact, the eyes E of the applied address signals A<0>-A<9> may even vary to such an extent that not all of the address signals are simultaneously valid at any time. In other words, there is no time during which the eyes E of all of the address signals overlap. Under these circumstances, the ideal address signals A<0>, A<1>, and A<9> signals, all of the address signals A<0>-A<9> cannot possibly be captured by the CLK signal. For example, in FIG. 2, the eye E of the A<0> signal from times t₀-t₃ does not overlap the eye of the A<9> signal from times t₅-t₇. It is therefore important to limit the jitter or timing skew of the CLK and address signals A<0>-A<9>.

Attempts have been made to solve the jitter problem exemplified by FIGS. 1 and 2 using various equalization techniques. Two different equalization approaches have been tried. The first approach attempts to modify the characteristics of the signal line by either making it less capacitive or by making a transmitted signal less affected by the capacitance, such as by inserting repeaters or inverters in the line. Unfortunately, this approach can unduly increase the cost of digital devices. The second approach attempts to modify the shape of the transmitted signal so that the capacitance of the signal line causes it to be received with close to its original shape. In one example, every transition of the digital signal is provided with a large overshoot, which is capacitively filtered out by the signal line. The size and complexity of circuitry using this approach can again unduly increase the cost of digital devices, particularly since the nature of the modification must depend on the characteristics of the bit pattern.

There is therefore a need for a relatively inexpensive system and method for allowing digital signals having an irregular bit pattern to be coupled through highly capacitive signal lines without causing jitter in the received signal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a timing diagram illustrating the manner in which signal jitter is created by coupling a digital signal through a highly capacitive signal line.

FIG. 2 is a timing diagram showing the manner in which timing skew or jitter can prevent a clock signal from capturing address signals during an “eye” when the address signals are valid.

FIGS. 3A and 3B are timing diagrams illustrating the manner in which signal jitter is avoided by a signal de-emphasis system and method according to one example of the invention.

FIG. 4 is a block diagram of a de-emphasis system according to one example of the invention.

FIG. 5 is a block diagram of a computer system using the de-emphasis system shown in FIG. 4 or a de-emphasis system according to some other example of the invention.

DETAILED DESCRIPTION

The manner in which a signal de-emphasis system and method according to one example of the invention avoids creating signal jitter is shown in FIGS. 3A and 3B. A digital signal that is to be transmitted through a highly capacitive signal line is shown in FIG. 3A. The signal is assumed to be referenced to a clock signal (not shown) that may be transmitted along with the signal. The signal is high for one clock period between times t₀ and t₁, is then low for one clock period between times t₁ and t₂, is high for three clock periods between times t₂ and t₅, low for one clock period between times t₅ and t₆, then high for one clock period between times t₆ and t₇, and finally low for two clock periods between times t₇ and t₉.

The de-emphasis system and method applies the digital signal to the signal line with the shape shown by the solid line in FIG. 3. As shown therein, when the digital signal is high, it is applied to the signal line with a level of V* volts for the first period of the clock signal, and it then transitions to V₁ volts for any remaining period of the clock signal. Similarly, when the digital signal is low, it is applied to the signal line with a level of 0 volts for the first period of the clock signal, and it then transitions to V₂ volts for any remaining period of the clock signal. Thus, when the digital signal is high for three clock periods between times t₂ and t₅, it is applied to the signal line as V* volts for the first clock period between times t₂ and t₃ followed by V₁ volts for the remaining two clock periods between times t₃ and t₅. When the digital signal is low for two clock periods between times t₇ and to, it is applied to the signal line as 0 volts for the first clock period between times t₇ and t₈ followed by V₂ volts for the remaining clock period between times t₈ and t₉.

The digital signal as it is received from the highly capacitive signal line at a downstream location is shown by the dotted line in FIG. 3B. The signal line charges toward V* volts between times t₀ and t₁, and reaches approximately V₁ volts after one clock period at time t₁. The digital signal is low during the next clock period between times t₁ and t₂, so the signal line begins discharging from V₁ volts toward 0 volts, and it reaches approximately V₂ volts after one clock period at time t₂. The signal line then begins charging from V₂ volts toward V* volts at time t₂. Therefore, the charging of the signal line always starts from V₂ volts, and the discharging of the signal line always starts from V₁ volts.

If the digital signal applied to the signal line is high for more than one clock period, e.g., between times t₂ and t₅, the signal line is again charged to voltage V₁ during the first clock period from times t₂ and t₃. However, during the next two clock periods between times t₃ and t₅, the signal line remains at V₁ volts because the digital signal applied to the signal line transitions from V* volts to V₁ volts after one clock period at time t₃. Therefore, the signal line always starts discharging from V₁ volts regardless of the number of clock period the digital signal is high. Similarly, when the signal line begins discharging from V₁ volts toward 0 Volts at time t₇, it again reaches approximately V₂ volts after one clock period at time t₈. During the next clock period between times t₈ and t₉, the signal line remains at V₂ volts because the digital signal applied to the signal line transitions from 0 volts to V₂ volts after one clock period at time t₈. Therefore, the signal line always starts charging from V₂ volts regardless of the number of clock period the digital signal is low. It can therefore be seen that the voltages between which the signal line is charged and discharged is the same regardless of the pattern of the digital signal applied to the signal line. For this reason, signal jitter of the type exemplified by FIGS. 1 and 2 does not occur.

A de-emphasis system 10 according to one example of the invention is shown in FIG. 4. The digital signal to be transmitted is applied to an input terminal 14 and is routed through two signal paths 16, 18. The first signal path 16 includes a multiplier 20 that multiples the digital signal by 1−D₁, where D₁ is the change in the digital signal after the first clock period that the signal remains high. In the example shown in FIG. 3, D₁ is equal to V*−V₁. For example, if D₁=0.25, the multiplier 20 multiplies the digital signal by 0.75. Therefore, if the digital signal transitions between 0 and 1 volts, the signal at the output of the multiplier 20 will transition between 0 and 0.75 volts.

The second signal path 18 includes a delay circuit 24 followed by a second multiplier 26. The delay circuit 24 delays the digital signal applied to the input terminal 14 by one clock period. The multiplier 26 multiples the digital signal by D₂, where D₂ is the change in the digital signal after the first clock period that the signal remains low. Although D₂ need not be equal to D₁, it will be assumed for purposes of illustration that such is the case. In the example shown in FIG. 3, D₂ is equal to V₂. If D₂ is also equal to 0.25, the multiplier will multiply the digital signal by 0.25.

The respective outputs of the multipliers 20, 26 are applied to a differential adder 30 that subtracts the output of the second multiplier 26 from the output of the first multiplier 20. The resulting output is applied to a level translator circuit 34. The level translator circuit 34 adds a fixed offset to the signal at the output of the adder 30, which, for purposes of illustration is presumed to be equal to D, where D=D₁=D₂. The voltage levels present in the de-emphasis circuit 10 referenced by the letters shown in FIG. 4 for the digital signal shown in FIG. 3 in which D₁=D₂=0.25 are as follows TABLE 1 Time A B C D E F t0 1 0.75  0 0 0 1 0.25 −0.25 0 1 0.75 0 0 0.75 1 1 0.75 1 0.25 0.5 0.75 1 0.75 1 0.25 0.5 0.75 0 0 1 0.25 −0.25 0 1 0.75 0 0 0.75 1 0 0 1 0.25 −0.25 0 0 0 0 0 0 0.25 1 0.75 0 0 0.75 1

It can be seen that column “F” of Table 1 corresponds to the voltage levels shown in the solid line in FIG. 3.

A computer system 50 using the de-emphasis system 10 shown in FIG. 4 is shown in FIG. 5. The computer system 50 includes a processor 52 for performing various computing functions, such as executing specific software to perform specific calculations or tasks. The processor 52 includes a processor bus 54 that normally includes an address bus, a control bus, and a data bus. In addition, the computer system 50 includes one or more input devices 54, such as a keyboard or a mouse, coupled to the processor 52 to allow an operator to interface with the computer system 50. Typically, the computer system 50 also includes one or more output devices 56 coupled to the processor 52, such output devices typically being a printer or a video terminal. One or more data storage devices 58 are also typically coupled to the processor 52 to allow the processor 52 to store data in or retrieve data from internal or external storage media (not shown). Examples of typical storage devices 58 include hard and floppy disks, tape cassettes, and compact disk read-only memories (CD-ROMs). The processor 52 is also typically coupled to cache memory 66, which is usually static random access memory (“SRAM”).

The computer system 50 also includes system memory 70, which is in the form of several registered double in-line memory modules (“DIMMs”) 74. Each of the DIMMs 74 includes a register 76 coupled to several dynamic random access memory (“DRAM”) devices 78 by a system of buses 80 that includes a command bus, an address bus and a data bus. The registers 76 each include a respective de-emphasis system 84 coupled to each of the address bus signals lines, which couple addresses to the DRAM devices 78. The de-emphasis system 84 may also be coupled to each of the command bus lines, which transmit memory commands to the DRAM devices 78. Finally, the de-emphasis system 84 may be coupled to each of the data bus lines, which transmit write data to the DRAM devices 78. Therefore, even though the signal lines of the buses 80 may be highly capacitive, the signals are transmitted from the registers 76 to the DRAM devices 78 with very low signal jitter.

Each of the DIMMs 74 is coupled to a memory controller 90, which is connected to the processor 52 through the processor bus 54. The DIMMs 74 are coupled to the memory controller 90 by a system of buses 92 that again includes a command bus, an address bus and a data bus. The memory controller 90 includes a de-emphasis system 94 coupled to each of the address bus signals lines for transmitted addresses to the DIMMs 74 with relatively low jitter. The de-emphasis system 94 may also be coupled to each of the command bus lines and the data bus lines for transmitting memory commands and write data, respectively, to the DIMMs 74 with relatively low jitter.

Although the present invention has been described with reference to the disclosed embodiments, persons skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention. Such modifications are well within the skill of those ordinarily skilled in the art. Accordingly, the invention is not limited except as by the appended claims. 

1. A system for de-emphasizing a digital signal having first and second logic levels before transmitting the de-emphasized digital signal, the system comprising a signal adjustment circuit having an input coupled to receive the digital signal, the signal adjustment circuit being operable to generate the de-emphasized digital signal with a first signal level for a first predetermined period in response to the digital signal transitioning from the first logic level to the second logic level and with a second signal level for as long as the digital signal is at the second logic level, the signal adjustment circuit being operable to generate the de-emphasized digital signal with a third signal level for a second predetermined period in response to the digital signal transitioning from the second logic level to the first logic level and with a with a fourth signal level for as long as the digital signal is at the first logic level.
 2. The system of claim 1 wherein the first and second predetermined periods are substantially equal to each other, and wherein the signal adjustment circuit comprises: a delay circuit receiving the digital signal and being operable to generate a delayed signal at an output terminal having a delay relative to the digital signal that is equal to the first and second predetermined periods; a first multiplier circuit that is operable to generate a first intermediate signal by multiplying the magnitude of the first and second logic levels of the digital signal by a first multiplier, a second multiplier circuit that is operable to generate a second intermediate signal by multiplying the magnitude of the first and second logic levels of the delayed signal by a second multiplier; and a combining circuit coupled to receive the first and second intermediate signals and to generate the de-emphasized digital signal by combining the first and second intermediate signals.
 3. The system of claim 2 wherein the first multiplier comprises 1−X and the second multiplier comprises X.
 4. The system of claim 3 wherein X comprises 0.25 so that the first multiplier comprises 0.75 and the second multiplier comprises 0.25.
 5. The system of claim 1 wherein the magnitude of the first signal level is substantially equal to the magnitude of the second logic level.
 6. The system of claim 1 wherein the magnitude of the third signal level is substantially equal to the magnitude of the first logic level.
 7. The system of claim 1 wherein the duration of the first predetermined period is equal to the duration of the second predetermined period.
 8. The system of claim 7 wherein the digital signal is synchronized to a clock signal, and wherein the first and second predetermined delays are substantially equal to one period of the clock signal.
 9. The system of claim 1 wherein the magnitude of the third signal level is substantially equal to the magnitude of the first logic level, and wherein the magnitude of the first signal level is substantially equal to the magnitude of the second logic level.
 10. The system of claim 1 wherein the magnitudes of the second and fourth signal levels are intermediate the magnitudes of the first and third signal levels.
 11. A de-emphasis system having an input terminal receiving a digital input signal, the de-emphasis system comprising: a delay circuit having an input terminal coupled to the input terminal of the de-emphasis system, the delay circuit being operable to generate a delayed signal at an output terminal having a predetermined delay relative to the digital input signal; a first signal adjustment circuit having an input coupled to receive the digital input signal from to the input terminal of the de-emphasis system, the first signal adjustment circuit being operable to generate a first digital output signal having first and second adjusted logic levels responsive to respective first and second logic levels of the digital input signal; a second signal adjustment circuit having an input coupled to receive the delayed signal from the output terminal of the delay circuit, the second signal adjustment circuit being operable to generate a second digital output signal having third and fourth adjusted logic levels responsive to respective first and second logic levels of the delayed signal; and a combining circuit coupled to receive the first and second digital output signals from the first and second signal adjustment circuits, respectively, the combining circuit being operable to generate a digital output signal having signal levels corresponding to the combination of the first and second digital output signals.
 12. The de-emphasis system of claim 11 wherein the combining circuit comprises a summing circuit that is operable to generate a digital output signal having signal levels corresponding to the magnitude of the first digital output signal less the magnitude of the second digital output signal.
 13. The de-emphasis system of claim 11 wherein the digital input signal is synchronized to a clock signal, and wherein the predetermined delay provided by the delay circuit comprises one period of the clock signal.
 14. The de-emphasis system of claim 11, further comprising a level shifting circuit coupled to receive the digital output signal from the summing circuit, the level shifting circuit being operable to shift the level of the digital output signal to generate a level shifted output signal.
 15. The de-emphasis system of claim 11 wherein the first signal adjustment circuit comprises a first multiplier circuit that is operable to generate the first and second adjusted logic levels of the first digital output signal by multiplying the magnitude of the first and second logic levels of the digital input signal by a first multiplier, and wherein the second signal adjustment circuit comprises a second multiplier circuit that is operable to generate the third and fourth adjusted logic levels of the second digital output signal by multiplying the magnitude of the first and second logic levels of the delayed signal by a second multiplier.
 16. The de-emphasis system of claim 11 wherein the first multiplier comprises 1−X and the second multiplier comprises X.
 17. The de-emphasis system of claim 16 wherein X comprises 0.25 so that the first multiplier comprises 0.75 and the second multiplier comprises 0.25.
 18. A processor-based system, comprising a system processor having a processor bus; a system memory operable to store write data and to retrieve read data at locations corresponding received address signals; a system controller coupled to the system processor through the processor bus, the system controller being coupled to the system memory and being operable to supply to the system memory the address signals each of which has first and second logic levels, the system controller including a de-emphasis system for de-emphasizing the address signals before transmitting the address signals to the system memory, the de-emphasis system having inputs coupled to receive the respective address signals and being operable to generate de-emphasized address signals that are supplied to the system memory, each of the de-emphasized address signals having a first signal level for a first predetermined period in response to the respective address signal transitioning from the first logic level to the second logic level and having a second signal level for as long as the respective address signal is at the second logic level, each of the de-emphasized address signals having a third signal level for a second predetermined period in response to the respective address signal transitioning from the second logic level to the first logic level and having a fourth signal level for as long as the respective address signal is at the first logic level; an input device coupled to the system processor through the system controller and the processor bus to allow data to be entered into the computer system; and an output device coupled to the system processor through the system controller and the processor bus to allow data to be output from the computer system.
 19. The processor-based system of claim 18 wherein the first and second predetermined periods are substantially equal to each other, and wherein the de-emphasis system comprises: a delay circuit receiving each of the address signals and being operable to generate respective delayed address signals at respective output terminals having a delay relative to the respective address signal that is equal to the first and second predetermined periods; a first multiplier circuit that is operable to generate first intermediate signals by multiplying the magnitude of the first and second logic levels of the respective address signals by a first multiplier, a second multiplier circuit that is operable to generate second intermediate signals by multiplying the magnitude of the first and second logic levels of the respective delayed signals by a second multiplier; and a combining circuit coupled to receive the first and second intermediate signals and to generate de-emphasized address for transmission to the system memory by combining each of the first and second intermediate signals generated from the same address signals.
 20. The processor-based system of claim 19 wherein the first multiplier comprises 1−X and the second multiplier comprises X.
 21. The processor-based system of claim 20 wherein X comprises 0.25 so that the first multiplier comprises 0.75 and the second multiplier comprises 0.25.
 22. The processor-based system of claim 19 wherein the magnitude of the first signal level is substantially equal to the magnitude of the second logic level.
 23. The processor-based system of claim 19 wherein the magnitude of the third signal level is substantially equal to the magnitude of the first logic level.
 24. The processor-based system of claim 19 wherein the duration of the first predetermined period is equal to the duration of the second predetermined period.
 25. The processor-based system of claim 24 wherein the address signals are synchronized to a clock signal, and wherein the first and second predetermined delays are substantially equal to one period of the clock signal.
 26. The processor-based system of claim 19 wherein the magnitude of the third signal level is substantially equal to the magnitude of the first logic level, and wherein the magnitude of the first signal level is substantially equal to the magnitude of the second logic level.
 27. The processor-based system of claim 19 wherein the magnitudes of the second and fourth signal levels are intermediate the magnitudes of the first and third signal levels.
 28. A method of de-emphasizing a digital signal having first and second logic levels before transmitting the de-emphasized digital signal, method comprising: in response to the digital signal transitioning from the first logic level to the second logic level, transmitting the de-emphasized digital signal with a first signal level for a first predetermined period; after the first predetermined period, transmitting the de-emphasized digital signal with a second signal level for as long as the digital signal is at the second logic level; in response to the digital signal transitioning from the second logic level to the first logic level, transmitting the de-emphasized digital signal with a third signal level for a second predetermined period; and after the second predetermined period, transmitting the de-emphasized digital signal with a fourth signal level for as long as the digital signal is at the first logic level.
 29. The method of claim 28 wherein the magnitude of the first signal level is substantially equal to the magnitude of the second logic level.
 30. The method of claim 28 wherein the magnitude of the third signal level is substantially equal to the magnitude of the first logic level.
 31. The method of claim 28 wherein the duration of the first predetermined period is equal to the duration of the second predetermined period.
 32. The method of claim 31 wherein the digital signal is synchronized to a clock signal, and wherein the first and second predetermined delays are substantially equal to one period of the clock signal.
 33. The method of claim 28 wherein the magnitude of the third signal level is substantially equal to the magnitude of the first logic level, and wherein the magnitude of the first signal level is substantially equal to the magnitude of the second logic level.
 34. The method of claim 28 wherein the magnitudes of the second and fourth signal levels are intermediate the magnitudes of the first and third signal levels. 